This invention relates to a class of digital communication systems known as asynchronous transfer mode (ATM) switching systems and generally to intercomputer communications architectures. More particularly, this invention relates to switch fabric-type architecture of an ATM switching element. The invention is not to be confused with a bus-type architecture of an ATM switching element. This invention is useful in telecommunications systems which require real-time routing and switching of digitized cells of data. A particular application is in the field of ISDN data switching at telephone central offices.
There is a need for high-speed switching and throughput in a telecommunications switch for digital communication applications wherein the primary usage is switching data between an external source or input resource and an external output or destination resource. Two types of architectures are known: bus architectures and switch-fabric architectures. Bus architectures provide multiple-point-to-multiple-point connections. Switch fabric architectures provide single-point-to-single-point connections.
A building block in a switch-fabric architecture ATM switch system is a structure known as a switch element. A switch element provides packet signal routing from one of a plurality of input ports to one or more of a plurality of output ports by maintaining an array of crosspoints for connecting any input port to any output port. Switch elements may be aggregated in various patterns to provide an arbitrarily large N by N possible interconnections of input ports to output ports, each via a unique path.
Problems arise where the receiving port cannot assimilate information as fast as it is delivered or where the priority of the traffic varies. A "brute-force" technique for handling the queuing problem is to provide sufficient data storage at each possible crosspoint in the switch element wherein if the amount of data accumulated at the crosspoint exceeds capacity of the data storage, data is discarded, thus forcing the destination port to request that data be resent. Such a solution is offered in the ATM self-routing switch element Model MB86680, an integrated circuit available from Fujitsu Microelectronics, Inc. of San Jose, Calif. A representation of this prior art switch element 1 is shown in FIG. 1. The element has a number of input terminals I1 to In (3, 5, 7) connected via crosspoints 31-39 to a number of output terminals O1 to On (9, 11, 13) through buffer memories 2, 4, 6, 8, 10, 12, 14, 16, and 18. The solution employed by prior art switch element 1 is very wasteful of crosspoint memory because each memory element is connected to just one crosspoint. Memory element 6, for example, can only store and buffer data traveling from input In to output O1. Depending on packet traffic through the switch element 1, memory at many of the crosspoints in the switch element 1 will not be needed, while at high traffic crosspoints more memory will be required than is provided in the switch element 1, and data packets will therefore have to be discarded. Discarding data packets is extremely wasteful of network resources because of the time and processing involved in the destination element requesting that the data packet be resent, and the subsequent retransmission of the data packets by the source element.
What is needed is an architecture and switching element that optimally uses available memory for queuing and buffering data packets at high-traffic crosspoints without slowing switching operations.